1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device which is fabricated in a highly dense layout while preventing interference between circuits which are formed therein.
2. Description of the Prior Art
FIG. 19 is a view showing a structure of an ordinary semiconductor integrated circuit device in which a logic circuit 200 is disposed between an input buffer part 300 and an output buffer part 100. A signal supplied to the semiconductor integrated circuit device is admitted to the input buffer part 300, processed at the logic circuit 200 and outputted from the output buffer part 100 to a point outside the semiconductor integrated circuit device.
FIG. 20 is a circuitry diagram showing an example of a structure of the output buffer part 100. The output buffer part 100 includes output buffers 1, 2 and 3 which have input terminals 111, 112 and 113, and output terminals 121, 122 and 123, respectively. All of the output buffers 1, 2 and 3 arc connected to a power source line 11 which supplies a potential VCC and to a power source line 21 which supplies a ground potential GND.
FIG. 21 is a circuitry diagram showing another example of a structure of the output buffer part 100. The illustrated output buffer part 100 includes output buffers 1, 2 and 4. The output buffer 4 has an input terminal 114 and an output terminal 124. All of the output buffers 1, 2 and 4 are connected to the power source line 11 which supplies the potential VCC and to power source line 21 which supplies ground potential GND. Further, the output buffer 4 is connected to a power source line 31 which supplies a potential VEE.
In recent years, as the semiconductor integrated circuit device has become faster and the driving capabilities of the output buffers 1 to 4 increase, a switching noise generated by the output buffers 1 to 4 becomes more detrimental to the circuit portion around the output buffers. In other words, when transferred to tile semiconductor integrated circuit device through the power source lines 11, 21 and 31, the switching noise could cause malfunction of the semiconductor integrated circuit device.
To eliminate the influence of the switching noise which is generated by the output buffers 1 to 4, the power source line which is connected to the output buffer part 100 is customarily separated from the power source lines which are connected to the logic circuit part 200 and the input buffer part 300. In addition, separation of the power source lines from each other is also necessary within the output buffer part 100 if a small amplitude interface needs be provided with the buffers or if both the TTL level and the ECL level are to be taken into account.
An instance of this is illustrated in FIG. 22 which diagrammatically shows that the power source lines are separated from each other within the output buffer part 100 which includes output buffers 1, 2 and 3 which have the same structure as those shown in FIG. 20. While the potentials VCC and GND are supplied to both output buffers 1 and 2 through the power source lines 11 and 12, respectively, power sources 12 and 22 are used to provide the output buffer 3 with the potentials VCC and GND. Thus, between the output buffers 1 and 2 and the output buffer 3, the power source lines are separated from each other.
FIG. 23 is a circuitry diagram showing where the power source lines are separated from each other within the output buffer part 100 which includes output buffers 1, 2 and 4 which have the same structure as those shown in FIG. 21. The output buffers 1 and 2 are both TTL type buffers which output a relatively large amplitude. The potentials VCC and GND arc supplied to these output buffers 1 and 2 through the power source lines 11 and 21, respectively. On the other hand, the output buffer 4 is an ECL type buffer which outputs a relatively small amplitude. While the potential VCC is supplied to the output buffer 4 through the power source line 11, which is the same with the output buffers 1 and 2, the potential GND is supplied to the output buffer 4 through the power source line 22. By thus isolating the power source line which provides the potential GND, a switching noise from the output buffers 1 and 2 which are each constructed as a TFL type buffer which outputs a relatively large amplitude is denied entry into the output buffer 4 which is structured as an ECL type buffer which outputs a relatively small amplitude.
FIG. 24 is a plan view showing wiring on the semiconductor in which the power source lines are separated from each other in the manner described above. FIG. 24 corresponds to the circuitry diagram of FIG. 22. The output buffer part 100 is formed in an area 101 and the power source lines 11, 12, 21 and 22 are disposed above the output buffer part 100. Thus, all power source lines which could be connected to the output buffers are formed in the area in which the output buffers are disposed so that the output buffers can be selectively connected to the power source lines. This arrangement is present in most semiconductor integrated circuit devices, and particularly, in most master-slice type semiconductor integrated circuits.
Having such a structure as above, the conventional semiconductor integrated circuit device requires that the buffer area be wide enough so that all the power source lines which could be connected to the buffers can be disposed in the buffer area. Hence, the power source lines 12 and 22 which will not be connected to the output buffer 1 are inevitably disposed above the output buffer 1, thereby unnecessarily increasing the width of the area which is demanded by the output buffer 1. This deteriorates the integration of the semiconductor integrated circuit device.
The deterioration in the integration is not only present in the output buffer area and the integration is deteriorated in an inner logic block as well. This is further disadvantageous if both a TTL circuit and an ECL circuit are to be formed in the inner logic block or if both a digital circuit and an analog circuit are to be formed in the inner logic block. In such a case, since the arrangement of the power source lines must be calculated early in the designing stage and a later change in the arrangement is not easily made, the designing freedom is low.
In other situations, due to a lengthy wiring from the power source lines or pads to the buffers, a resistance or inductance component could adversely affect the semiconductor integrated circuit device.